Chandrakasan Publications

Recent Selected Journal Papers (2016-current)

Maji S., U. Benerjee, S. H. Fuller, A. P. Chandrakasan, “A Threshold-Implementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. [link]

Maji S., U. Banerjee, S. H. Fuller, R. T. Yazicigil, A. P. Chandrakasan, “Securing Embedded Medical Devices using Dual-Factor Authentication,” IEEE International Symposium on Computer-Based Medical Systems (CBMS), Jun. 2021. [link]

Banerjee U., A. P. Chandrakasan, “A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021. [link]

Maji S., U. Banerjee, A. P. Chandrakasan, “Leaky Nets: Recovering Embedded Neural Network Models and Inputs through Simple Power and Timing Side-Channels – Attacks and Defenses,” IEEE Internet of Things Journal, Feb. 2021. [link]

Jeong T., A. P. Chandrakasan, H. S. Lee, “S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance,” CICC 2020. [link]

Maji S., U. Banerjee, S. H. Fuller, M. R. Abdelhamid, P. M. Nadeau, R. T. Yazicigil, A. P. Chandrakasan, “A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices,” CICC 2020. [link]

Ibrahim M. I., M. I. W. Khan, C. S. Juvekar, W. Jung, R. T. Yazicigil, A. P. Chandrakasan, R. Han, “THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz,” ISSCC 2020. [link]

Hills G., C. Lau, A. Wright, S. Fuller, M. D. Bishop, T. Srimani, P. Kanhaiya, R. Ho, A. Amer, Y. Stein, D. Murphy, Arvind, A. P. Chandrakasan, M. M. Shulaker, “Modern microprocessor built from complementary carbon nanotube transistors,” Nature, vol. 572, no. 7771, pp.595-602, Aug. 2019. [link]

Banerjee U., T. S. Ukyab, A. P. Chandrakasan, “Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols,” IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2019, no. 4, pp. 17-61, Aug. 2019. [link]

Biswas A., A. P. Chandrakasan, “CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks,” IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp.217-230, Jan. 2019. [link]

Juvekar C., V. Vaikuntanathan, A. P. Chandrakasan, “GAZELLE: A Low Latency Framework for Secure Neural Network Inference,” USENIX Security Symposium, August 2018. [link]

Tikekar M., V. Sze, A. P. Chandrakasan, “A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices,” IEEE Journal of Solid-State Circuits, vol. 53, no. 8, pp.2368-2377, Aug. 2018. [link]

Mimee M., P. Nadeau, A. Hayward, S. Carim, S. Flanagan, L. Jerger, J. Collins, S. McDonnell, R. Swartwout, R. J. Citorik, V. Bulovic, R. Langer, G. Traverso, A. P. Chandrakasan, T. K. Lu, “An ingestible bacterial-electronic system to monitor gastrointestinal health,” Science, vol. 360, no. 6391, pp.915-918, May 2018. [link]

Price M., J. Glass, A. P. Chandrakasan, “A Low-Power Speech Recognizer and Voice Activity Detector Using Deep Neural Networks,” IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp.66-75, Jan. 2018. [link]

Paidimarri A., A. P. Chandrakasan, “A Wide Dynamic Range Buck Converter With Sub-nW Quiescent Power,” IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp.3119-3131, Dec. 2017 [link]. 

El-Damak, D., A. P. Chandrakasan, “A 10 nW-1μW Power Management IC With Integrated Battery Management and Self-Startup for Energy Harvesting Applications,” IEEE Journal of Solid-State Circuits, vol. 51, no. 4. pp.943-954, April 2016. [link]

Complete publications list