In Your Community: Meet Anantha Chandrakasan
From Berkeley researcher to EECS department head
They told him that it wouldn’t work. “When we went to conferences, they did not believe that complex digital circuits could reliably operate at low voltages.”
Then a graduate student at the University of California, Berkeley, Professor Anantha P. Chandrakasan wasn’t entirely sure it would work either.
In the end, though, his low-power chip designs did work, and one year later, Chandrakasan gave one of the most influential talks in the history of the International Solid-State Circuits Conference. So many people attended that some couldn’t even get close enough to hear, so the organizers asked him to give the talk a second time — a first for the conference.
Batteryless energy harvester
Running electronics on body heat
MIT researchers have demonstrated a wearable power generator that uses the difference in temperature between your skin and the surrounding air – even just a couple of degrees – to produce a small, steady flow of power to run your medical monitor or your Bluetooth® headset. No need for a battery.
In the wearable power generator, a commercially available “thermal harvester” turns the temperature difference into electricity, but the generated voltage and current are tiny. The MIT solution: a novel “interface circuit” that boosts that tiny voltage to a useful level, keeps it constant despite temperature changes, and delivers the highest-ever fraction of the power from the harvester to the device.
Chandrakasan named head of electrical engineering and computer science
Succeeds Grimson as leader of MIT's largest academic department
Anantha P. Chandrakasan, the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering, has been named the next head of the Department of Electrical Engineering and Computer Science (EECS). He will assume the new role beginning July 1.
Chandrakasan will take over the role previously held by Eric Grimson, who was named MIT's chancellor in February. EECS is the largest academic department at MIT; nearly 30 percent of undergraduates major in the department's programs.
"As the largest academic department in the School of Engineering, and at MIT, EECS and its faculty are involved in an exceptional range of intellectual, educational, and research activities," School of Engineering Dean Ian Waitz said today (June 13) in an email to the EECS community. "I welcome the new ideas that Anantha will bring to leading EECS and his dedication as he assumes this role."
TI and MIT develop a 0.6 volt DSP in 28-nanometer processaimed at delivering Ultra-Low Power for next-generation multimedia and computing experiences
Aimed at delivering Ultra-Low Power for next-generation multimedia and computing experiences
SAN FRANCISCO, Feb. 22, 2011 /PRNewswire/ -- Texas Instruments Incorporated (TI) (NYSE: TXN) and the Massachusetts Institute of Technology (MIT) today presented a joint research paper detailing design methodologies for a 28-nanometer (nm) mobile applications processor at the 2011 International Solid-State Circuits Conference (ISSCC). The paper—"A 28nm 0.6V Low Power Digital Signal Processor (DSP) for Mobile Applications"—demonstrates that a DSP is capable of scaling from high-performance mode at 1.0 volts down to an ultra-low power (ULP) mode at 0.6 volts (V). This DSP is one of the first system-level, low voltage, 28nm designs for the mobile device market, demonstrating TI's continued commitment to enabling lower power and extended battery life in mobile devices running advanced applications.
"As the multimedia and computing capabilities of TI's OMAP™ platform-based smartphones, tablets and other mobile devices increase, there is a continually expanding gap between performance demands and battery capacity," said Gordon Gammie, Distinguished Member of the Technical Staff at TI and ISSCC presenter. "TI believes that 28nm process technology advancements, developed in tandem with TI and MIT's low power circuit and methodology collaboration, gives us the right knowledge base to successfully meet the next-generation processing demands within the future mobile power envelope."
ISSCC: Algorithm paves path to better video
SAN FRANCISCO – A Texas Instruments researcher described a parallel approach to handling current and future compression standards.
The parallel algorithm described in a paper at the International Solid State Circuits Conference could become part of High Efficiency Video Coding (HVEC ), the follow on to today's H.264/AVC standard. The work promises significant improvements in the quality and power consumption for tomorrow's systems that create or play video on anything from 3-D TVs to mobile handsets.
The HEVC effort aims to deliver by January 2013 a successor to today's mainstream H.264/AVC standard. It targets a 50 percent improvement in coding efficiency, enabling Quad Full HD video resolutions of up to 4,096 x 2,160 pixels.